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Origin and Onyx2 Theory of Operations Manual
(document number: 007-3439-002 / published: 1998-06-15)    table of contents  |  additional info  |  download
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Glossary

100Base-TX

See Fast Ethernet.

adaptive routing

A mechanism by which different messages can be routed to the same destination through different paths.

Application-Specific Integrated Circuit (ASIC)

Integrated circuit designed for a specific task.

asynchronous

Transfer of information in which the source and target are not synchronized. See also synchronous.

Asynchronous Transfer Mode (ATM)

Networking standard for transfer of multimedia data (voice, graphics, video). Specifies exchange of data through standardized, fixed-length cells. Because cells are uniform, they can be switched efficiently across many types of LANs and WANs.

B

byte, as in MB (megabyte)

b

bit, as in Mb (megabit)

bandwidth

Capacity to pass data. Usually measured as megabytes per second (MB/sec).

bidirectional

Transfer of information in both directions.

Bridge chip

An ASIC that converts the XIO protocol to PCI protocol. A Bridge chip is contained on an XIO board. See also .

cache coherence

Mechanism that ensures that cached copies of memory locations are kept consistent.

Challenge

Architecture used in previous high-end systems.

CrayLink Interconnect

(1) Interconnection fabric that links Node boards. Consists of high-speed links and, for 4P and larger configurations, routers. (2) Protocol used at the message layer in CrayLink Interconnect and within the Hubs for high-speed transfer of messages between Node boards. See also Node board, Link Level Protocol (LLP), Positive ECL (PECL), physical layer, STL, and Crossbow chip.

crossbar

Switching circuit that creates multiple point-to-point connections. Also referred to as “n x n switch,” or “n-by-n switch”; it keeps n items communicating at full-speed with n other items.

Crossbow chip

An 8-port ASIC that controls the dataflow through the set of XIO links. Contains a crossbar and circuits for flow control, routing, and arbitration. Depending on the type of system, one or two Crossbow ASICs are located on the module midplane. See also crossbar, micropacket, and XIO.

Crosstown Converter (XC) chip

ASIC that converts STL protocol to PECL, and vice versa.

Crosstown Converter board

An XIO board that connects XIO interface to an external chassis. Crosstown interface is required, for instance, to connect an Origin2000 module to a graphics chassis. Contains an XC chip and connectors for external cabling.

DIMM

Dual In-Line Memory Module

directory memory

A dedicated memory array on each Node board which supports the Origin2000 cache-coherence protocol (directory-based cache coherence). The system uses directory memory to track caches that contain a particular data item. If a change is made to the data item, all processors that are caching that location and that are indicated by the directory are notified. See also Distributed Shared-Memory, and cache-coherence.

Distributed Shared-Memory (DSM)

Main memory that is both distributed and shared. For systems that employ DSM, sections of main memory are distributed with each processor. Although distributed, each section of main memory is accessible by all processors through an interconnection fabric.

Fast Ethernet

Any of several standards for 100 Mbit/sec Ethernet (for example, 100Base-T, 100Base-TX). Each uses the same collision detection scheme (CSMA/CD) but uses a different transmission medium or message format.

Fast 20

A 16-bit wide differential SCSI bus running at a peak transfer rate of 40 MB/sec.

Fiber Distributed Data Interface (FDDI)

Networking standard for a fiber-optic LAN. Specifies a ring network with up to 1000 access points. The circumference of ring can be up to 120 miles, and the maximum baud rate is 100 Mbit/sec.

full-size (FS) XIO board

Form-factor (the shape) of a full-size I/O board. Dimensions of an FS XIO board are 10.5 x 1 3x 1 in.

g

giga (billion): 109, or 1,000,000,000, as in gB (one billion bytes)

G

giga: 230, or 1,073,741,824, as in GB (1,073,741,824 bytes)

half-size (HS) XIO board

Form-factor (the shape) of a half-size I/O board. Dimensions of an HS XIO board are 10.5 x 6.5 x 1 in.

High Performance Parallel Interface (HIPPI)

A high-speed interface used over relatively short distances. It was developed at Los Alamos National Laboratory and is now ANSI-standard X3T9/88-127. HIPPI is ideal for transfer of large volumes of data.

HIMM

Horizontal In-Line Memory Module. In a deskside or rackmounted configuration, this module holds processor and memory and is connected to the Node board.

hop count

Number of Router ASICs a message must pass through to go from source to target node. See also micropacket and Router board.

Hub chip

ASIC that is the interface controller on Node board. It contains four major Node board subsystems: processor interface(s), memory and directory interface, I/O (XIO) interface, and CrayLink Interconnect. See also CrayLink Interconnect, and XIO.

hyper-

Existing in a space of one or more dimensions. See also hypercubes.

hypercubes

Mathematical model that defines n-dimensional cubes. For Origin2000 configurations, all topologies are either a hypercube (up to 64P) or fat hypercube (fatcube; 128P).

interconnection fabric

A set of switches in a given topology (hypercube, mesh, etc.) that interconnect the nodes of a system.

IOC3 chip

ASIC that converts the PCI protocol to standard I/O protocols; for example, converts PCI to Ethernet, serial, or parallel. The IOC3 receives its input from the Bridge ASIC. See also Bridge chip and IO6 board.

I06 board

An XIO board that provides Origin2000 with basic I/O functions; for example, Ethernet, serial, and SCSI ports. Can contain the Bridge, MIO, or IOC3 chip. See also XIO.

IP27

Product title for the Node board on Origin2000 System.

IP29

Product title for the motherboard on the Origin200 System.

k

kilo (thousand): 103, or 1,000, as in kB (one thousand bytes)

K

kilo: 210, or 1024, as in KB (1024 bytes)

LAN (Local Area Network)

A geographically-limited data communications network that allows interconnection of terminals, microprocessors and computers, usually within physically-adjacent buildings. Ethernet and FDDI are examples of LANs.

latency

Amount of time it takes to complete a request and receive a reply (typically to memory, or to an I/O device).

LINC chip

An ASIC designed to support intelligent controllers on some XIO devices; for instance, ATM, HIPPI.

Link Level Protocol (LLP)

A protocol that handles error-checking and error-recovery to ensure error-free transmission of data across all CrayLink Interconnect and XIO links. See XIO, CrayLink Interconnect, Router chip.

m

mega (million): 106, or 1,000,000, as in mB (one million bytes)

M

mega: 220, or 1,048,576, as in MB (1,048,576 bytes)

MAC

Media Access Control; messages sent over a LAN have a unique six-byte identifier called a MAC.

message

Unit of information transfer.

messaging

Means by which information is transferred; or, the act of transferring information.

Meta Router

A module that contains up to eight Router boards and is used to form the metacube level of interconnection in Origin2000 for systems having more than 32 routers.

micropacket

Format of data transferred over the link layer within CrayLink Interconnect and XIO. A micropacket is the minimum size of data transfer, and error-checking is made over micropacket quantities. A micropacket consists of two 64-bit doublewords of data, and two 16-bit halfwords of control information. The control information includes check bits, sequence numbers (transmit and receive), and an 8-bit sideband.

The data portion of a micropacket contains a message header and optional message data. The 8-bit sideband is used by the message layer for framing and flow control. Together, the sideband and data portion of a micropacket can be considered a message segment. Micropackets are encoded when a message is injected into the LLP module which encapsulates the CrayLink Interconnect and XIO links.

When passing from the link layer to the physical layer, micropackets are converted from 64 bits to 16 bits. This 16-bit data is transmitted at 400 MHz, which is four times the core data rate of 100 MHz, by the Source Synchronous Driver (SSD). The data is demultiplexed by the Source Synchronous Receiver (SSR).

modular

Constructed from standardized units. In the case of Origin2000, modules are configurable in the field.

module, Origin2000

Enclosure that contains Origin2000 components, such as Node, XIO, graphics, and Router boards. There are two configurations of Origin2000 modules: server and graphics.

multiprocessing

Simultaneous processing by two or more processors in one computer system.

node

Functional unit in Origin2000 module that contains processors, memory, XIO interface, and CrayLink Interconnect interface. Physically, a node is implemented on a Node board.

Node board

Board that contains a node of the Origin2000 system. Each Node board has one or two R10000 processors with their cache(s), a section of main memory with its dedicated directory memory, an interface to system I/O, and an interface to the CrayLink Interconnect. Subsystems on the Node board are connected through a large ASIC called the Hub chip. See also. See also Hub chip, R10000 chip, CrayLink Interconnect.

Non-Uniform Memory Access (NUMA)

A characteristic of DSM systems. In DSM systems, sections of main memory are located at various distances from a given processor. As a result, memory access times (latencies) can be non-uniform. See also Distributed Shared-Memory and latency.

null-Router

Jumper board used to connect two Node boards directly to each other in a 4P system.

PCAR

External expansion module for industry-standard PCI boards.

Peripheral Component Interconnect (PCI)

I/O standard for connection of system peripherals. Specifies a PCI bus whose major features include: multiple bus masters (boards arbitrate to “own” the bus); autoconfiguration (bus is configured automatically); high peak bandwidth
(264 MB/sec); interrupt sharing among boards.

PIMM

Processor Included Memory Module. In an entry-level configuration, this module holds processor and memory and is connected to the Node board.

physical layer

Layer within CrayLink Interconnect and XIO protocols that establishes physical link over the transmission medium. See also CrayLink Interconnect, transmission medium, and XIO.

Positive ECL (PECL)

Differential signal levels that are used in external cables for CrayLink Interconnect and XIO (Crosstown) interconnections.

protocol

Set of rules that governs the transfer of information.

R10000 chip

Fifth-generation MIPS Rx000-series processor. Also called the T5. The R10000 is based on RISC 64-bit 4-way superscalar technology and is contained on a single chip (whereas, for instance, the R8000® processor is a multichip module).

Router board

Board that contains the Router chip, associated circuits and a CrayLink Interconnect port. For expandable systems, one Router board is required for each two nodes. See also Router chip.

Router chip

ASIC that routes messages on CrayLink Interconnect. Contains crossbar and circuits for flow control, routing, and arbitration, and is physically located on a Router board. See also crossbar, Router board, and CrayLink Interconnect.

scalable

A situation in which one item increases in proportion to another. For example, CrayLink Interconnect is scalable; as you add nodes to the interconnection fabric, you increase CrayLink Interconnect capacity and performance. Origin2000 systems are scalable with respect to cost; an entry-level system has a low fixed cost, and the system cost scales as you add more processors.

SGI Transistor Logic (STL)

High-speed, low-voltage, unidirectional signals used for communication between ASICs inside a module. STL signals can be converted to PECL signals for communicating between modules over a cable. See also Positive ECL (PECL), physical layer, and XIO.

SIMM

Single In-line Memory Module

source

Sender of a message. See also target.

source synchronous

A transmission in which clock accompanies data.

STL

See SGI Transistor Logic (STL)

synchronous

A transmission of data in which both source and target are synchronized.

system, Origin200

An Origin2000 system is composed of one or two towers, within which are either one or two processor/memory daughtercards mounted on a motherboard and containing main and directory memory. The Origin200 system has three PCI slots. In a dual-tower configuration, the two towers can be linked by the CrayLink Interconnect.

system, Origin2000

An Origin2000 system is composed of one or more server or graphics modules, within which processor/memory nodes are linked by an interconnection fabric.There are two types of system: deskside, and rackmounted. See also module, Origin2000.

system controller

A board that monitors and controls system functions (for example, system cooling and power consumption). There are two levels of system controller: entry-level, and Multi-Module System Controller.

T5

See R10000 chip.

target

Receiver of a message. See also source.

topology

A pattern of interconnection between nodes. In Origin2000, n-dimensional versions of a hypercube topology are used to link nodes into a coherent system.

transmission medium

Conductor(s) over which signals are passed.

VME

I/O standard for connection of system peripherals. Specifies a bus called VMEbus. Predates PCI.

widget

A generic term for any device connected to an XIO port.

Wormhole Routing

In wormhole routing, a message that passes through the switches of the interconnection network is referred to as a “worm,” since it can be segmented into micropackets. The worm can stretch across several nodes and links at any one time. As soon as the head is received, each intermediate switch moves it towards the intended port without waiting for the entire message to arrive. See also adaptive routing.

XIO

(1) The interconnection in each Origin2000 module that provides Node boards with access to I/O devices. Controlled by Crossbow chip. (2) Protocol used on XIO interface. Implements high-speed transfer of messages across connections established by Crossbow. Runs over LLP at the link layer and STL at the physical layer. See also crossbar, Crossbow chip, micropacket, and CrayLink Interconnect.

Origin and Onyx2 Theory of Operations Manual
(document number: 007-3439-002 / published: 1998-06-15)    table of contents  |  additional info  |  download

    Front Matter
    About This Guide
    Chapter 1. Overview of the Origin Family Architecture
    Chapter 2. Origin Family Boards
    Chapter 3. Origin Family ASICs
    Glossary
    Index


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