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 Linux Device Driver Programmer's Guide,Porting to SGI Altix Systems
(document number: 007-4520-007 / published: 2008-09-24)    table of contents  |  additional info  |  download
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64-bit address support
64-bit Address and Data Support

Acquire semantics
Acquire Semantics

Address management
Linux Kernel and User Virtual Address Management

Address mapping
DMA
DMA Address Mapping
PIO
PIO Address Mapping

Address space
64-bit
System Memory Address Space
System Memory Address Space
AMO
AMO Space
bus virtual
PIO Addresses and DMA Addresses
cacheable memory
Cacheable Memory Space
CPU access
CPU Access to I/O Address Space - Programmable I/O (PIO)
CPU Access to Memory or I/O Address Space
DMA
Anatomy of a Mapped DMA Address
global MMR
Global MMR Space
physical
Physical Address Space
SHub physical
SHub Physical Address Map
supported
Address Spaces Supported
system memory
System Memory Address Space
user virtual mapping
Directly Mapping User Virtual Addresses

AMO space
AMO Space

Architecture
interrupt
Interrupt Architecture
PIO
PCI-X I/O and Memory Resources
system components
System Components
system memory address space
System Memory Address Space

Atomic memory operation (AMO)
AMO Space

BaseIO
PX-brick with BaseIO (IX-brick)

Bus
adapter
PIO Addresses and DMA Addresses
arbitration
Bus Arbitration
virtual address
PIO Addresses and DMA Addresses

Cache coherency
Cache Use

Cacheable memory space
Cacheable Memory Space

Compute/processor node
Compute/Processor Node (SC-brick)

Configuration register
Configuration Register Initialization

Device driver
byte-range memory allocation
Allocating Byte-Range Memory
disabling validity checking
Disabling Validity Checking
memory allocation
Device Driver Memory Allocation
for specific nodes
Allocating Page Boundary Memory on Specific Nodes
page boundary
Allocating Page Boundary Memory
memory usage
Device Driver Memory Usage
user memory area access
Accessing the User Memory Area

Direct Memory Access (DMA)
See DMA

DMA
32-bit direct mapped addresses
Format of 32-bit Direct Mapped DMA Addresses
32-bit page mapped addresses
Format of 32-bit DMA Page Mapped Addresses
64-bit mapped addresses
Format of a 64-bit DMA Mapped Adddress
access to system physical memory space
Device Access to System Physical Memory Space - Direct Memory Access
address management
PCI-X DMA Address Management
addresses
PIO Addresses and DMA Addresses
addressing
DMA Addressing
addressing extension
DMA Addressing Extension
architecture
PCI-X Direct Memory Access (DMA)
consistent mappings
Consistent DMA Mappings
mapped address anatomy
Anatomy of a Mapped DMA Address
mapped routines
PCI-X DMA Mapped Routines
streaming mappings
Streaming DMA Mappings
types of mappings
Types of DMA Mappings

Execution delay
long
Delaying Execution -- Long Delay
short
Delaying Execution -- Short Delay

Global MMR space
Global MMR Space

Interrupt request
See IRQ

Interrupt signals
Interrupt Signal Distribution

Interval Timer Counter (ITC)
Interval Timer Counter (ITC)

IRQ
driver registration
Driver Interrupt Registration
management
Interrupt Request (IRQ) Management

IX-brick
System Components
PCI-X with BaseIO (IX-brick)
PX-brick with BaseIO (IX-brick)

Latency and operation order
Latency and Operation Order

Legacy functionality
Legacy Functionality

Memory
allocation for device drivers
Device Driver Memory Allocation
allocation for page boundary
Allocating Page Boundary Memory
allocation for specific nodes
Allocating Page Boundary Memory on Specific Nodes
byte-range allocation
Allocating Byte-Range Memory
fencing
Memory Fencing
ordering
Memory Ordering
user access
Accessing the User Memory Area

Memory access
from CPU
CPU Access to Memory or I/O Address Space
from devices
Device Access to System Physical Memory Space - Direct Memory Access
to device registers
CPU Access to I/O Address Space - Programmable I/O (PIO)

Node, compute/processor
Compute/Processor Node (SC-brick)

PCI/PCI-X
configuration space
PCI/PCI-X Configuration Space
device attachment
PCI-X Device Attachment
DMA address management
PCI-X DMA Address Management
DMA mapped routines
PCI-X DMA Mapped Routines
implementation
PCI-X Implementation
interrupt mechanism
PCI-X Interrupt Mechanism
I/O and memory resources
PCI-X I/O and Memory Resources
I/O resource management
PCI-X I/O Resource Address
I/O resource use macros
PCI-X I/O Resource Use Macros
local node
Targeting a PCI-X Device on a Local Node
locating device programmatically
Programmatically Locating Your PCI Device
locating information physically
Physically Locating Your PCI Device Information
logical address
Logical Address of Your PCI Device
memory resource address
PCI-X Memory Resource Address
memory resource use macros
PCI-X Memory Resource Use Macros
origin
PCI-X Device Attachment
physical location
Physical Location of Your PCI Device
remote node
Targeting a PCI-X Device on a Remote Node
resource reservation
PCI-X I/O Resource Reservation
system initialization
PCI System Initialization
unsupported signals
Unsupported PCI-X Signals

PCI-X
with BaseIO
PCI-X with BaseIO (IX-brick)
with expansion
PCI-X with Expansion (PX-brick)

Peripheral Component Interconnect
See PCI/PCI-X

Physical address space
Physical Address Space

PIO
address anatomy
Anatomy of a PIO Address
address mapping
PIO Address Mapping
address translation
PIO Address Translation from CPU to PCI Bus
addresses
PIO Addresses and DMA Addresses
addressing
PIO Addressing
addressing extension
PIO Addressing Extension
architecture
PCI-X I/O and Memory Resources
CPU access
CPU Access to I/O Address Space - Programmable I/O (PIO)
mapped addresses
PIO Addresses
operation flow
Flow of PIO Operation
resource management
PCI-X PIO Resource Management
write operations
PIO Write (Posted) Synchronization

Programmable I/O
See PIO

PX-brick
System Components
PCI-X with Expansion (PX-brick)
PX-brick with BaseIO (IX-brick)

PX-brick expansion
PX-brick Expansion

Registers
ITC
Interval Timer Counter (ITC)

Release semantics
Release Semantics

Routines, DMA mapped
PCI-X DMA Mapped Routines

SC-brick
Compute/Processor Node (SC-brick)
PX-brick Expansion

SHub physical address map
SHub Physical Address Map

System physical memory space
Device Access to System Physical Memory Space - Direct Memory Access

Time management
interval timer counter (ITC)
Interval Timer Counter (ITC)

User virtual addresses
Directly Mapping User Virtual Addresses

Validity checking
Disabling Validity Checking

Write operations
Programmable I/O Write Operations

Prev Table of Contents 
Appendix A. Memory Operation Ordering on SGI Altix Systems   

Linux Device Driver Programmer's Guide,Porting to SGI Altix Systems
(document number: 007-4520-007 / published: 2008-09-24)    table of contents  |  additional info  |  download

    Front Matter
    New Features in This Guide
    About This Guide
    Chapter 1. Introduction
    Chapter 2. Architecture
    Chapter 3. PCI-X Device Attachment
    Chapter 4. PCI System Initialization
    Chapter 5. Finding Your PCI Device
    Chapter 6. PCI/PCI-X Configuration Space
    Chapter 7. PCI-X I/O and Memory Resources
    Chapter 8. PCI-X Interrupt Mechanism
    Chapter 9. PCI-X Direct Memory Access (DMA)
    Chapter 10. Device Driver Memory Usage
    Chapter 11. Time Management
    Chapter 12. Building Linux Kernels and Modules
    Appendix A. Memory Operation Ordering on SGI Altix Systems
    Index


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