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MIPS R10000 Microprocessor User Guide, Version 2.0
(document number: 007-2490-001 / published: 1997-01-30)
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1. Introduction to the R10000 Processor
1.1 MIPS Instruction Set Architecture (ISA)
MIPS has defined an instruction set architecture (ISA), implemented in the following sets of CPU designs:
The original MIPS I CPU ISA has been extended forward three times, as shown in
Figure 1-1; each extension is backward compatible. The ISA extensions are inclusive; each new architecture level (or version) includes the former levels.
*1
Figure 1-1 MIPS ISA with Extensions
The practical result is that a processor implementing MIPS IV is also able to run MIPS I, MIPS II, or MIPS III binary programs without change.
Copyright 1996, 1997, MIPS Technologies, Inc. -- 09 DEC 96
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MIPS R10000 Microprocessor User Guide, Version 2.0
(document number: 007-2490-001 / published: 1997-01-30)
table of contents | additional info | download
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