5. Secondary Cache Interface
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ECC is supported for both the data and tag arrays to improve data integrity.
Figure 5-1 Secondary Cache Data and Tag Array
The secondary cache is implemented as a two-way set associative, combined instruction/data cache, which is physically addressed and physically tagged, as described in Chapter 4, the section titled "Cache Organization and Coherency."
The SCSize mode bits specify the secondary cache size; minimum secondary cache size is 512 Kbytes and the maximum secondary cache size is 16 Mbytes, in power of 2 (512 Kbytes, 1 Mbyte, 2 Mbytes, etc.).
The 
