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MIPS R10000 Microprocessor User Guide, Version 2.0
(document number: 007-2490-001 / published: 1997-01-30)
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18. Cache Test Mode

A.9 Free List and Busy Registers
A
busy-bit table indicates whether or not a result has been written into each of the physical registers. Each register is initially defined to be busy when it is moved from the
free list to the active list; the register becomes available ("not busy") when its instruction completes and its result is stored in the register file.
The busy-bit table is read for each operand while an instruction is decoded, and these bits are written into the queue with the instruction. If an operand is busy, the instruction must wait in the queue until the operand is "not busy." The queues determine when an operand is ready by comparing the register number of the result coming out of each execution unit with the register number of each operand of the instructions waiting in the queue.
With a few exceptions, the integer and address queues have integer operand registers, and the floating-point queue has floating-point operand registers.

Copyright 1996, 1997, MIPS Technologies, Inc. -- 09 DEC 96



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MIPS R10000 Microprocessor User Guide, Version 2.0
(document number: 007-2490-001 / published: 1997-01-30)
table of contents | additional info | download
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