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MIPS R10000 Microprocessor User Guide, Version 2.0
(document number: 007-2490-001 / published: 1997-01-30)
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18.6 Cache Test Mode Protocol
Normal Read Protocol
A cache test mode
normal read operation reads a selected RAM array. The read address, way, and array are specified by the read command.
The external agent issues a normal read command by:
- driving the address on SysAD(57:46)
- driving the way on SysAD(45)
- negating the auto-increment select on SysAD(44)
- negating the Write/Read select on SysAD(43)
- driving the array select on SysAD(42:40)
- asserting SysVal* for one SysClk cycle.
After a read latency of 15
PClk cycles, the processor provides the read response by:
- entering Master state
- driving the read data on SysAD(39:0)
- asserting SysVal* for one SysClk cycle.
In the following
SysClk cycle, the processor reverts to
Slave state.
Normal reads have a repeat rate of 17 PClk cycles.
Figure 18-5 depicts two cache test mode normal reads.
Figure 18-5 Cache Test Mode Normal Read Protocol
Copyright 1996, 1997, MIPS Technologies, Inc. -- 09 DEC 96
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MIPS R10000 Microprocessor User Guide, Version 2.0
(document number: 007-2490-001 / published: 1997-01-30)
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