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MIPS R10000 Microprocessor User Guide, Version 2.0
(document number: 007-2490-001 / published: 1997-01-30)
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17. CPU Exceptions
17.7 COP2 Instructions
If the CU2 bit of the CP0 Status register is not set during an attempted execution of such Coprocessor 2 instructions as COP2, LWC2, SWC2, LDC2, and SDC2, the system takes a Coprocessor Unusable exception.
In the R4400 processor, if the CU2 bit is set, COP2 instructions are handled as NOPs; the operations of Coprocessor 2 load/store instructions are undefined. In the R10000 processor, an execution of a Coprocessor 2 instruction takes a Reserved Instruction exception when CU2 bit is set.
Copyright 1996, 1997, MIPS Technologies, Inc. -- 09 DEC 96
  
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MIPS R10000 Microprocessor User Guide, Version 2.0
(document number: 007-2490-001 / published: 1997-01-30)
table of contents | additional info | download
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