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MIPS R10000 Microprocessor User Guide, Version 2.0
(document number: 007-2490-001 / published: 1997-01-30)    table of contents  |  additional info  |  download
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17.3 TLB Refill Vector Selection

Cold Reset Exception


Cause

The Cold Reset exception is taken for a power-on or "cold" reset; it occurs when the SysGnt* signal is asserted while the SysReset* signal is also asserted.*1 This exception is not maskable.

Processing

The CPU provides a special interrupt vector for this exception:

The Cold Reset vector resides in unmapped and uncached CPU address space, so the hardware need not initialize the TLB or the cache to process this exception. It also means the processor can fetch and execute instructions while the caches and virtual memory are in an undefined state.

The contents of all registers in the CPU are undefined when this exception occurs, except for the following register fields:

  • In the Status register, SR and TS are cleared to 0, and ERL and BEV are set to 1. All other bits are undefined.
  • Config register is initialized with the boot mode bits read from the serial input.
  • The Random register is initialized to the value of its upper bound.
  • The Wired register is initialized to 0.
  • The EW bit in the CacheErr register is cleared.
  • The ErrorEPC register gets the PC.
  • The FrameMask register is set to 0.
  • Branch prediction bits are set to 0.
  • Performance Counter register Event field is set to 0.
  • All pending cache errors, delayed watch exceptions, and external interrupts are cleared.
Servicing

The Cold Reset exception is serviced by:

  • initializing all processor registers, coprocessor registers, caches, and the memory system
  • performing diagnostic tests
  • bootstrapping the operating system



Copyright 1996, 1997, MIPS Technologies, Inc. -- 09 DEC 96


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MIPS R10000 Microprocessor User Guide, Version 2.0
(document number: 007-2490-001 / published: 1997-01-30)    table of contents  |  additional info  |  download


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