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MIPS R10000 Microprocessor User Guide, Version 2.0
(document number: 007-2490-001 / published: 1997-01-30)    table of contents  |  additional info  |  download
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16.3 Virtual Address Translation

Format of a TLB Entry

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Figure 16-5 shows the TLB entry formats for both 32- and 64-bit modes. Each field of an entry has a corresponding field in the EntryHi, EntryLo0, EntryLo1, or PageMask registers, as shown in Chapter 14, Coprocessor 0; for example the PFN and uncached attribute (UC) fields of the TLB entry are also held in the EntryLo registers.

Figure 16-5 Format of a TLB Entry

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Copyright 1996, 1997, MIPS Technologies, Inc. -- 09 DEC 96

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MIPS R10000 Microprocessor User Guide, Version 2.0
(document number: 007-2490-001 / published: 1997-01-30)    table of contents  |  additional info  |  download

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