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 MIPS R10000 Microprocessor User Guide, Version 2.0
(document number: 007-2490-001 / published: 1997-01-30)    table of contents  |  additional info  |  download
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1.6 R10000 Pipelines

Stage 1

In stage 1, the processor fetches four instructions each cycle, independent of their alignment in the instruction cache -- except that the processor cannot fetch across a 16-word cache block boundary. These words are then aligned in the 4-word Instruction register.

If any instructions were left from the previous decode cycle, they are merged with new words from the instruction cache to fill the Instruction register.

Copyright 1996, 1997, MIPS Technologies, Inc. -- 09 DEC 96

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MIPS R10000 Microprocessor User Guide, Version 2.0
(document number: 007-2490-001 / published: 1997-01-30)    table of contents  |  additional info  |  download


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