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14. Coprocessor 0
Format: TLBR Description: The G bit (which controls ASID matching) read from the TLB is written into both of the EntryLo0 and EntryLo1 registers. The EntryHi and EntryLo registers are loaded with the contents of the TLB entry pointed at by the contents of the TLB Index register. In the R4400, this instruction had to be executed in unmapped spaces, and in the R10000 processor it can be executed in unmapped spaces without any hazard. In addition, TLBR can be executed in mapped spaces. Operation: Exceptions: Coprocessor unusable exception
Description:
The G bit (which controls ASID matching) read from the TLB is written into both of the EntryLo0 and EntryLo1 registers.
The EntryHi and EntryLo registers are loaded with the contents of the TLB entry pointed at by the contents of the TLB Index register.
In the R4400, this instruction had to be executed in unmapped spaces, and in the R10000 processor it can be executed in unmapped spaces without any hazard. In addition, TLBR can be executed in mapped spaces.
Operation:
Exceptions:
Coprocessor unusable exception
MIPS R10000 Microprocessor User Guide, Version 2.0 (document number: 007-2490-001 / published: 1997-01-30) table of contents | additional info | download
