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MIPS R10000 Microprocessor User Guide, Version 2.0
(document number: 007-2490-001 / published: 1997-01-30)    table of contents  |  additional info  |  download
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14.22 CacheErr Register (27)

CacheErr Register Format for Primary Instruction Cache Errors

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Figure 14-24 shows the format of the CacheErr register when a primary instruction cache error occurs.

Figure 14-24 CacheErr Register Format for Primary Instruction Cache Errors

EW: set when CacheErr register is already holding the values of a previous error

D: data array error (way1 || way0)

TA: tag address array error (way1 || way0)

TS: tag state array error (way1 || way0)

PIdx: primary cache virtual block index, VA[13:6]

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0: Reserved. Must be written as zeroes, and returns zeroes when read.

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Copyright 1996, 1997, MIPS Technologies, Inc. -- 09 DEC 96

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MIPS R10000 Microprocessor User Guide, Version 2.0
(document number: 007-2490-001 / published: 1997-01-30)    table of contents  |  additional info  |  download

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