10. CACHE Instructions
in the primary data cache to Invalid. VA[13:5] defines the address and VA[0] defines the way to be invalidated.
The invalidation takes place by writing the following bits:
- primary data cache state bits are set to 00 (Invalid)
- the SCWay bit is set to 0
- the StateMod bits = 001 (Normal)
- the state parity is set to 0.
The LRU bit does not change.
If the StateMod of the block to be invalidated = 0102 (Inconsistent), the block in the primary data cache must be written back to the secondary cache.
The address and way in the secondary cache to be written back to are read out of the primary data cache tag address and secondary way fields and all 32 bytes are written back.
Only the data field of the secondary cache is modified by this instruction since the processor follows state and data subset rules.
Since the CE bit is not defined in the R10000 processor, this instruction no longer has a CP0 ECC register mode.
