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MIPS R10000 Microprocessor User Guide, Version 2.0
(document number: 007-2490-001 / published: 1997-01-30)
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9.12 System Interface Error Protection and Handling
Error Protection
The System interface buses have the following error protection schemes, as listed in Table 9-7.
Table 9-7 System Interface Bus Error Protection
Copyright 1996, 1997, MIPS Technologies, Inc. -- 09 DEC 96
  
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MIPS R10000 Microprocessor User Guide, Version 2.0
(document number: 007-2490-001 / published: 1997-01-30)
table of contents | additional info | download
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