7. Clock Signals
cache, to allow pipelined accesses.
The processor provides 6 pairs of differential clock outputs, SCClk(5:0) and SCClk*(5:0), to be used by the secondary cache synchronous SRAMs. These outputs swing between VccQSC and Vss. The SCClkTap mode bits (Mode bits are described in Chapter 8, the section titled "Mode Bits.") specify the alignment of SCClk(5:0) and SCClk*(5:0) relative to the internal secondary cache clock. Note that the output buffer delay is not included.
The secondary cache interface clock is generated by dividing down the internal processor clock, PClk.
SCClk is related to SysClk according to the following formula:
SCClk = SysClk*(SysClkDiv+1)/(SCClkDiv+1)
For example, in a 50 MHz system with SysClkDiv=7 and SCClkDiv=2,
SCClk = 50*8/3 = 133 MHz.
