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Hardware » Books » Developer »
MIPS R10000 Microprocessor User Guide, Version 2.0
(document number: 007-2490-001 / published: 1997-01-30)
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6.11 System Interface Flow Control
External Data Response Flow Control
Since the processor has an incoming buffer, an external agent may supply external data response data in adjacent SysClk cycles, without regard to cache bandwidth or internal resource availability.
Copyright 1996, 1997, MIPS Technologies, Inc. -- 09 DEC 96
  
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MIPS R10000 Microprocessor User Guide, Version 2.0
(document number: 007-2490-001 / published: 1997-01-30)
table of contents | additional info | download
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