1.3 What is an R10000 Microprocessor?

The R10000 processor is a single-chip superscalar RISC microprocessor that is a follow-on to the MIPS RISC processor family that includes, chronologically, the R2000, R3000, R6000, R4400, and R8000.

The R10000 processor uses the MIPS ANDES architecture, or Architecture with Non-sequential Dynamic Execution Scheduling.

The R10000 processor has the following major features (terms in bold are defined in the Glossary):

it implements the 64-bit MIPS IV instruction set architecture (ISA)

it can decode four instructions each pipeline cycle, appending them to one of three instruction queues

it has five execution pipelines connected to separate internal integer and floating-point execution (or functional) units

it uses dynamic instruction scheduling and out-of-order execution

it uses speculative instruction issue (also termed "speculative branching")

it uses a precise exception model (exceptions can be traced back to the instruction that caused them)

it uses non-blocking caches

it has separate on-chip 32-Kbyte primary instruction and data caches
it has individually-optimized secondary cache and System interface ports
it has an internal controller for the external secondary cache
it has an internal System interface controller with multiprocessor support

The R10000 processor is implemented using 0.35-micron CMOS VLSI circuitry on a single 17 mm-by-18 mm chip that contains about 6.7 million transistors, including about 4.4 million transistors in its primary caches.

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MIPS R10000 Microprocessor User Guide, Version 2.0
(document number: 007-2490-001 / published: 1997-01-30) table of contents | additional info | download

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